L'importanza delle memorie nella filiera AI. IL ciclo proseguirà?

Technological focus: why memory became central to AI systems

• AI compute is constrained not only by GPUs/ASICs/TPUs, but increasingly by memory capacity and memory bandwidth—the so-called “memory wall.”
• Traditionally, DRAM/NAND were viewed as cyclical, commodity-like markets driven by oversupply/undersupply cycles (including capex timing lag that leads to price drops and rebounds).
• With AI, the thesis is that the cycle is changing:
  • Memory demand is tied to large, multi-year data center buildouts and training + inference infrastructure.
  • Demand becomes more persistent, with strong emphasis on HBM (High Bandwidth Memory).

HBM and the architecture described (core tutorial-like explanation)

• AI workloads offload computation to accelerators (GPU/ASIC). In simplified terms:
  • The GPU performs the “reasoning/calculation.”
  • Model weights/activations and data must be pulled from HBM close to the GPU.
  • This reduces latency and prevents the memory wall from worsening.

HBM definition

• HBM = DRAM-based stacked “piles”, progressing through generations (e.g., HBM3 → HBM4).
• An interposer (described as a “data highway”) connects multiple HBM stacks to the compute chip.
• The example discussed mentions stacking up to ~4 HBM stacks.

HBM3 vs HBM4 packaging/technology

• HBM3
  • Earlier packaging approach using stacking and techniques such as microbumps (described in the discussion generally as microbump-like methods).
• HBM4
  • Moving toward hybrid bonding using copper-to-copper (“copper on copper”) rather than solder-like microbump methods.
  • Goal: improve transport speed/bandwidth.

Advanced packaging ecosystem

• TSMC is highlighted as a leader in advanced packaging (including approaches like chip-on-substrate for GPUs and similar systems).
• ASML is referenced as an example of advanced lithography machinery used to support yield/capability (with CXMT risk discussed separately).
• ASE is mentioned as part of the packaging/testing ecosystem (along with other packaging/testing names referenced later).

DRAM vs NAND clarification (analogy for memory type relevance)

The video uses an analogy:

• DRAM: fast, volatile working memory (like ingredients on a table while cooking).
• NAND: slower non-volatile storage (like a cellar/archive).

Argument: NAND isn’t suitable for keeping GPU reasoning supplied due to latency, so HBM/DRAM remain crucial for the AI compute loop.

Market analysis: how multiples and cyclicality are interpreted

• The speakers argue that investors still label memory producers as cyclicals, but valuation suggests the market expects a peak followed by later collapse (e.g., discussion around an EPS peak around ~2028 and then decline).
• Their counterpoint: AI changes the demand curve because:
  • AI capex has already moved through “phase one” infrastructure,
  • and multi-year contracts increase demand visibility.
• Valuation theme:
  • Memory makers allegedly trade at lower-than-historical P/E multiples versus non-cyclical growth due to fear of cyclic collapse.
  • Thesis: AI could sustain revenue growth more through volume growth (not necessarily margin expansion).

Key company/industry players mentioned (with technological role)

Memory manufacturers

• Samsung
  • Strong integrated player; diversification helps shift capacity toward higher-margin memory like HBM.
• SK hynix
  • Emphasized for HBM and advanced memory focus.
• Micron
  • Referred to as recovering; also compared on revenue/cash/commitments.
• CXMT (Chinese)
  • Treated as a newer wildcard with state support.

Why CXMT is treated as risky (execution/yield focus)

• The discussion emphasizes that HBM-grade memory depends heavily on advanced lithography equipment and yields.
• Claim: CXMT remains closer to DUV rather than EUV manufacturing, reducing yield (example cited: ~60% yield vs higher yield expected with EUV).
• Conclusion: even if CXMT can produce chips, cost/yield disadvantages make it less attractive for HBM/GPU-adjacent stacks “right now.”

Advanced packaging / hybrid bonding / manufacturing enablers

• TSMC — advanced packaging
• Besi/B semiconductor — highlighted for focus on hybrid bonding
• ASML — EUV/DUV lithography machine leader (used to frame the technology gap affecting yields)
• Testing — later Q&A mentions:
  • Advantest
  • Tecnoprobe
  • Also framed with a “full 3-year investment cycle” perspective

Pricing cycle scenario + inference-driven demand growth

Potential near-term downside drivers:

• Customer “rationalization” (buy less quantity, manage memory more efficiently).
• Possible unit price compression if Chinese supply ramps (including a CXMT dumping risk).

Counter-argument:

• AI inference (not only training) increases memory usage and could drive total demand much higher.
• The speakers cite an estimate that memory usage could rise ~30–50x versus today, specifically for inference/automation needs.

Resulting expectation:

• Multiples may expand as volumes grow,
• even if ASP stabilizes or compresses.

Sector extensions: photonics and future infrastructure bottlenecks

• After memory, the next projected constraint is energy + heat + interconnect bandwidth.
• The video discusses progression toward photonic/optoelectronic interconnects:
  • Copper links may be replaced by optical fiber / photonics between racks/data center blocks and within systems.
  • Examples of optoelectronics/photonic supply chain mentioned:
    • Coherent
    • Lumentum
    • Sienna
• Also discussed: data center power/voltage scaling
  • Mention of a higher system voltage class (e.g., “800V”)
  • Importance of temperature sensors/management ICs (names include STM and competitors)

Additional product/industry concept: “HBM + NAND” hybrid path

• A later topic discusses “HBM + NAND” as a joint venture / hybrid memory concept.
• The speakers suggest it could:
  • reduce costs,
  • improve energy efficiency.
• However, they argue it likely won’t instantly erase the market for existing memory types—more of an evolution/merge than a full replacement.

Review/tutorial/guide angle (what the speakers “teach”)

This is presented less as a single-device review and more as a market-and-technology tutorial, combining:

1. Cyclicity explanation of DRAM (capex timing creates swings).
2. HBM architecture walkthrough (GPU ↔ HBM ↔ interposer, bandwidth, “memory wall”).
3. HBM3 → HBM4 packaging change (hybrid bonding / copper-to-copper).
4. DRAM vs NAND roles for AI training/inference.
5. Valuation interpretation (low multiples vs AI inference sustaining volumes).
6. Supply-chain mapping (memory makers + packaging + testing + lithography + photonics).

Main speakers / sources

Speakers/Hosts

• Andrea Cartisano (main host)
• Marco (guest; referenced frequently)
• Francesco (alias “Renegade”; guest)

Other sources referenced in the discussion

• TrendForce (memory price graphs/market data framing)
• ASML (referenced as EUV lithography equipment leader)
• Viridian Research (named as a channel/service with performance tracking and dashboards)
• Multiple “analysts” are cited regarding AI infra/inference demand, but no single consistent named report beyond the above is referenced.