Backend Lab 3 : NAND Gate

Main ideas / lessons

The lecture walks through building and verifying a 2-input NAND gate in an EDA flow:

1. Create schematic (transistor-level design).
2. Simulate schematic (SPICE).
3. Create layout matching the schematic (transistor placement + contacts + routing).
4. Run design checks (DRC/ERC/NCC) to ensure layout correctness and consistency with the schematic.
5. Simulate layout and compare timing results (rise/fall).
6. (Optional/extra) Create an icon/symbol for the NAND gate and show how to reuse it in new cells for simulation.

Key conceptual distinction

• Device naming (e.g., M1, M2) is different from assigning the SPICE model (done via setting the spice model on the selected device). Don’t confuse these.

Verification workflow (what each check does)

• DRC: Finds layout connectivity/geometry problems (spacing, overlaps, dangling arcs).
• ERC: Checks electrical rules / semiconductor well connections.
• NCC: Confirms schematic and layout match (netlist consistency).

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Step-by-step methodology

A) Initial setup and NAND schematic creation

Adjust the interface

• Ensure the message window is visible to view errors.
• Arrange windows: tile horizontally; tile message window with edit window.

Create design objects

• Create a new library named “nand gate”.
• Create a new cell:
  • Schematic cell named “nand”.

Build the NAND transistor schematic

• Start with an inverter/inverter-like structure:
  • 2 pMOS in parallel
  • 2 nMOS in series
  • Power source, ground, and off-page nodes for input/output.
• Flip/arrange transistors:
  • Select pMOS devices and mirror left-right.
• Connect devices carefully:
  • Use left-click/right-click to connect terminals.
  • Incomplete/incorrect wiring can look “almost connected” but leave gaps.
• Understand node/wire intersection behavior:
  • Wires “intersect” only when a DOT node is created between them.

Configure transistor parameters

• Open each device’s Object Properties (shortcut: Ctrl+I).
• Set transistor width (W) (set to 10 for each transistor; apply to all related devices).

Assign SPICE model correctly

• Set spice model using:
  • Tools → Simulation → Spice → set spice model
• Mentioned behavior:
  • Pressing W while a device is selected triggers spice model assignment.
• Distinguish from naming:
  • Naming devices as M1, M2 is NOT the same as assigning a SPICE model.

Prepare inputs/outputs

• For applying signals to wires:
  • Rename a wire (wire can act as a net for existing code).
• For applying signals through off-page nodes:
  • Export the node (create an export for the node’s name).
• Export signals:
  • Example: create exports for input/output node naming (e.g., output export named AB in the described flow).

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B) Schematic error checking and SPICE simulation

Run layout-style checks on the schematic

• Tools → DRC → check hierarchically
  • Confirm no errors/warnings initially.
• If errors occur:
  • Use the message window + stepping with < / > keys.
  • Example error: “arc dangles” (open arc).
  • Fix by removing/repairing dangling connections.
• If unnecessary pins appear:
  • Use Edit → Clean up cell → Clean up pins everywhere.

Write SPICE code

• Insert multiline spice code (misc spice code editor).
• Define:
  • Power: vdd (Electric treats the supply as VDD, and ground as global ground; explicit naming often not needed).
  • Input sources:
    • VA: PWL waveform with specified rise/fall/on/off timing.
    • VB: another PWL waveform.
• Timing meaning:
  • The PWL timing corresponds to delayed input behavior (e.g., input delayed by 10 ns, with rise/fall 10 ns, on-time and off-time 30 ns each).

Measure rise/fall

• Use a .measure-style statement:
  • Measure TR (rise) and TF (fall) using threshold crossing conditions (e.g., trigger when input crosses 4.5 V; fall/rise when output crosses 1).

Run simulation

• Add:
  • .tran transient analysis (e.g., 200 ns).
  • Include model file:
    • .do include (with C5 models directory; capitalization matters for C).
• Run:
  • Tools → Simulation → SPICE → (run)

View results and confirm NAND behavior

• Plot plane A B (inputs and output traces).
• Interpret NAND behavior:
  • Output transitions correlate with input transitions.
  • Output behaves like an inverter depending on which input is changing.
• Logic behavior is confirmed by matching output transitions to input changes.

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C) Layout creation (matching the schematic)

Create layout cell

• New cell with layout view:
  • Same cell name as schematic (e.g., “nand”, but layout).

Place transistor devices

• Place 2 pMOS and 2 nMOS.
• For each:
  • Rotate nMOS appropriately (rotate 90°).
  • Duplicate devices via Ctrl+C / Ctrl+V placement.
• Assign spice models:
  • Tools → Simulation → Spice → set spice model for all placed devices.

Make text/model visible

• Adjust device text size (e.g., text size set to 2) and confirm units so it displays clearly.

Assign electrical terminals via layout geometry

• Identify source/drain sides for each transistor visually.
• Arrange them per NAND topology:
  • pMOS configured in parallel to VDD
  • nMOS configured in series to ground

Create contacts and interconnect structure

• Use P active contacts:
  • Place contacts connecting pMOS sources to VDD.
• Add active regions/contacts to connect:
  • pMOS ↔ nMOS internal node
  • nMOS ↔ GND
• Insert metal routes using arcs/wires.

Adjust transistor dimensions

• Set minimum sizes:
  • Transistor W set to 10 (via object properties).
  • For contacts, adjust Y size similarly (contact width/height constraints apply).

Configure technology/design rules/preferences

• Edit → Preferences → Technology
  • Verify correct MOS technologies present.
  • Confirm metal layers count (e.g., 3 metal layers).
• Verify Design rules:
  • Confirm scale (e.g., select scale 300).
• Proceed with layout only after preferences and rules are correct.

Routing guidance

• When connecting:
  • Click a device terminal and connect to the intended contact terminal.
• Arc alignment:
  • Misalignment can cause thicker arcs (undesired geometry).
• Use Ctrl+G for grid snapping.

Layout error correction loop

• Run Tools → DRC → check hierarchically
• Fix errors such as:
  • spacing too close
  • overlaps
  • minimum width/height
  • notch layer n/p transistor overlaps/geometry
• Iterate until DRC reports no errors.

Ensure semiconductor “wells” exported (ERC step)

• Tools → ERC → check Wells
• If wells are not exported:
  • Export VDD and ground (e.g., export as vdd, ground, plus required output net export naming).

Run NCC (netlist consistency check)

• Perform NCC check between schematic and layout views.
• If NCC errors appear:
  • Fix mismatched export names (e.g., schematic output AB but layout output out).
  • Fix mismatched connections (e.g., pMOS drain connected to wrong drain/source node relative to schematic).
• Re-run DRC/ERC/NCC until:
  • netlist sync passes (no netlist errors).

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D) Simulate and compare schematic vs layout timing

Reuse the SPICE testbench

• Copy the earlier SPICE code and run it for layout-based extraction.

Compare measured metrics

• Measure rise/fall time from the transient and .measure results.
• Check correctness by comparing values and ensuring the correct edges are transitioning.
  • Example schematic: fall ≈ 1.9 ns, rise ≈ 2.1 ns
  • Example layout: measured values should match expected behavior.

Conclusion

• Layout and schematic are confirmed working, and timing values match as expected.

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E) Create a reusable NAND icon/symbol and reuse in new cells

Generate an icon view

• View → Make icon view
• Modify the initial icon into a nAND gate:
  • Delete/adjust the polygon.
  • Add inverter bubble (circle).
  • Use edit mode toggles to outline/pencil edit.
  • Control rotation with Ctrl+J to orient the bubble.

Create new cells for higher-level simulation

• Create a new schematic cell (e.g., “nand Sim”).
• Drag the NAND icon into the new cell.
• For simulation convenience:
  • Provide inputs as wire-connected nets rather than double-clicking arcs/nodes.
• Update SPICE testbench:
  • Ensure wire names match (A, B, AB).
• Repeat similarly for a layout-based top cell if desired (e.g., “nand layout sim”).

Benefit explicitly stated

• Separating simulation cells preserves the original schematic/layout cells from being modified.

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Speakers / sources featured

• Single speaker: The lecture narrator/instructor (name not provided in subtitles).
• Software/EDA tools referenced (as sources, not people):
  • Electric VLSI (cells, DRC/ERC/NCC, arc dangles, object properties, technologies, metal layers, C5 model includes)
  • SPICE simulator within Electric (Tools → Simulation → Spice)
  • C5 SPICE models included via .do include from a C5 models directory