Build a DIY full-frame CCD camera

Summary of technological concepts, build features, and findings

• Project goal: A DIY full-frame CCD camera prototype that aims to minimize mechanical complexity by using an electronic shutter instead of a mechanical one.

Viewfinder approach

• The build skips rangefinder and mirror/SRR construction due to difficulty.
• It uses an electronic viewfinder (screen preview).
• Tradeoffs noted:
  • Higher power consumption
  • Potential latency
  • Outdoor visibility limitations

Lens / mount strategy

• Uses a manual-lens workflow.
• Selects a lens mount (e.g., M mount / mirrorless flange distance short) to avoid reverse-engineering lens protocols.

Sensor choice (core hardware)

• Employs industrial/repurposed Kodak KII / “Ki 11000” 11MP interline-transfer CCD sensors with a full-frame optical imaging area.
• Key stated characteristics:
  • 11 megapixels
  • Global electronic shutter via interline transfer
  • 35mm full-frame optical format
  • Uses a CCD timing integration with Analog Devices (ADI) via an AFE/ADC timing generator
• Specific chip mention:
  • ADI AFE + ADC with integrated timing generator, paired with CCD timing/signal generation.

Clarification: “full-frame” here refers to the entire sensor area used for light sensing elements, not only the lens/35mm naming.

Timing / driving electronics approach

• CCD operation requires six clock signals.
• Instead of generating signals externally, the design uses an ADI integrated IC that:
  • Generates required CCD clocks/timing from a single input/control side
  • Performs amplification, sampling, and ADC conversion
  • Minimizes external circuitry
• High-level CCD readout concept:
  • Electronic front curtain clears charges
  • Exposure builds charge
  • Interline transfer moves charge into storage wells for a global shutter
  • Vertical clocking shifts rows to a buffer
  • Horizontal clocking shifts pixels out individually to the output/readout path

Power + signal level challenge

• CCD input voltages are not compatible with typical 3.3V/5V logic, so the system uses:
  • Multiple split-rail DC converters
  • Linear regulators
  • MOSFETs for heavy-load/fast-edge clock driving
    • Example: >100 pF load vertical clocks with <1 µs rise time
  • A 4053 analog multiplexer used as a logic shifter/switching utility for flexible routing

Processing platform

• Uses an NXP i.MX RT1176 microcontroller for main control.
• The ADI CCD timing/analog front-end handles analog signal complexities.
• Other architectures were discussed conceptually (e.g., CMOS vs CCD, FPGA timing generation, SoC+FPGA options), but the builder chose the ADI approach for an initially “straightforward” path.

Display / interface hardware

• A 4-inch 720×720 capacitive touchscreen serves as the electronic viewfinder.
• UI includes real-time shutter control feedback (e.g., sensitivity/ISO not implemented).

PCB and manufacturing workflow (practical notes)

• PCB manufactured using JLCPCB:
  • Recommends installing the JLCPCB plugin for one-click production file generation
  • Uses JLCPCB assembly service for some components
• The prototype board is described as experimental, including shortcuts such as:
  • Limited/no careful SDRAM routing detail
  • Not following all layout rules (e.g., a mentioned “3W rule”)
• Despite layout compromises, it works sufficiently for testing.

Enclosure approach

• A temporary/test enclosure is designed for rapid assembly and sensor testing.
• Uses JLC for 3D printing for a smoother workflow than local FDM setup.

Firmware/software bring-up approach

Screen side initialization

• Requires initialization sequences and power-table setup (e.g., PS LUT / related configuration).
• Video mode configuration resembles RGB-like modes.

CCD configuration

• Requires writing many register settings.
• With only a datasheet available (no application notes/examples), the builder relied on:
  • Re-reading the manual repeatedly
  • Trial-and-error to infer timing/register behavior
• This took longer than expected; an FPGA approach could theoretically speed up waveform generation.

First capture results and calibration issues

• Initial imaging works but shows issues:
  • Monochrome until colors are handled (initially missing color channel assignment)
  • Inverted orientation/direction due to lens + image processing orientation
  • Wrong size/geometry because the CCD readout uses dual-channel from left and right and storage alternates channels without correct layout handling
• Color handling explanation:
  • Not a 3-chip CCD system; it’s single-color-per-pixel with missing color information.
  • Software performs demosaicing/interpolation after capture (not deeply detailed).

Performance bottleneck + workaround

• Readout speed limits live view/capture rate:
  • ADC at 24 MHz
  • With dual channels: ~48 megapixels/second
  • For 11MP frames: theoretical baseline of about 4+ fps
• Mitigation:
  • Skip some lines to reduce effective resolution
  • Cannot skip pixels within a line, so horizontal resolution stays fixed
  • Targeting ~25 FPS by reducing to roughly 240p-level effective resolution
• Shutter speed changes currently affect live view frame rate (software/code issue noted).

Capture + storage workflow

• Touch UI triggers capture:
  • Saves captured images to SD card
• No built-in export tools yet:
  • Uses a PC utility for basic post-processing/preview.

Documentation / future plans

• Next improvements planned:
  • UI improvements
  • More photos
  • Behind-the-scenes stories
• A part two is mentioned, focusing on improvements to the current design.

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Main speakers / sources

• Primary speaker: The project creator/host (long-time electronics DIYer and photographer) who discusses the build throughout the video.
• Sponsored/source referenced: JLC PCB (sponsorship) and the JLCPCB plugin / assembly service for manufacturing workflow.
• Technical sources referenced:
  • Analog Devices (ADI) CCD AFE/ADC + timing generator IC
  • NXP i.MX RT1176 microcontroller
  • Kodak CCD sensor modules (Kodak KII / “Ki 11000 CM” sensors)
  • Texas Instruments / NXP-style peripheral reference: 4053 analog multiplexer
  • Harwin for connectors
  • SD card / PC utility mentioned for post-processing