STM32H5 workshop - 07 I3C interface theory and practice (beginners)

Summary of STM32H5 Workshop - 07 I3C Interface Theory and Practice (Beginners)

Overview of I3C Interface

I3C (Improved Inter-Integrated Circuit) is a standardized communication protocol designed to overcome limitations of traditional I²C, such as limited speed and the need for external interrupt signals.

I3C maintains compatibility with I²C but introduces new features and naming conventions:

• Roles: Controller (instead of Master) and Target (instead of Slave).
• Defined by MIPI Alliance’s MPP specification; the basic spec is freely available upon registration.
• Uses a two-wire interface (SDA and SCL) similar to I²C but introduces push-pull driving mode after arbitration, enabling higher speeds (up to 12.5 MHz, comparable to full-speed USB).

Key Features of I3C

• Push-Pull Driving Mode: Allows faster communication by switching from open-drain to push-pull mode after arbitration. The controller dynamically manages internal pull-up resistors. The clock line is push-pull driven, so clock stretching is not supported.

• Dynamic Address Assignment: Targets receive 7-bit addresses dynamically based on unique 64-bit IDs. This supports priority and discovery of devices on the bus.

• Common Command Codes (CCC): Standardized commands for common operations reduce the need to study individual sensor datasheets.

• In-Band Interrupts: Targets can initiate communication to notify the controller asynchronously and can send payloads with interrupts (e.g., for timing control).

• Advanced Features:

  • Group addressing (multicast)
  • Hot-join mechanism for devices powering up during bus operation
  • Secondary controller role switching

Compatibility and Limitations with I²C

• Not all I²C devices strictly follow the specification, which may cause issues.
• I3C high-speed mode relies on a 50 ns spike filter on the clock line, which may not be present in all I²C slaves.
• Clock stretching is disallowed in I3C.
• Some addresses are reserved for I3C use.
• Legacy I²C mode is supported but with some constraints.
• Signal integrity and bus design become more critical at higher speeds.

Advantages of I3C

• Higher data rates (up to 12.5 MHz in SDR mode).
• Reduced pin count due to in-band interrupts.
• Lower power consumption enabled by push-pull mode.
• Open standard with freely available basic specification.
• Potential for future extensions like multiple data lines and double data rate (not supported on STM32H5 currently).

Practical Demonstration Using STM32H5 and LSM6DSO Sensor

Hardware:

• STM32H5 MCU with NUCLEO board and IKS01A3 sensor extension shield (contains LSM6DSO sensor supporting I3C).

Required Modifications:

• Remove jumpers to isolate sensors on the bus.
• Account for level shifters (1.8V sensors vs 3.3V board), which limit maximum frequency.

Software Setup:

• Use STM32CubeIDE and STM32CubeMX for project configuration.
• Enable I3C peripheral in controller mode with mixed bus timing to accommodate level shifters.
• Configure interrupts and GPIO pins (PB8, PB9 for I3C; PA4 for sensor interrupt).
• Use STM32Cube Expansion Package (X-CUBE-MS) for sensor middleware.
• Override default I²C functions to support I3C communication.

Demo Behavior:

• Successful enumeration of sensor on I3C bus.
• Sensor detects vibration (wake-up event) and triggers LED blinking via in-band interrupt.

Code Walkthrough:

• Initialization of I3C peripheral and dynamic address assignment.
• Handling of enumeration success/failure callbacks.
• Read/write register functions implemented using low-level I3C transfers.
• Interrupt handling verifies events triggered by sensor activity.

Takeaways

• I3C offers significant speed improvements and power savings over I²C.
• Its open specification may lead to broader adoption.
• Compatibility with I²C devices is mostly maintained but requires careful consideration.
• Future enhancements like multi-line data buses and double data rate could further increase throughput.
• STM32H5 series supports I3C with embedded pull-ups and push-pull clock driving.
• Practical implementation requires some workarounds and careful timing configuration, especially when using level shifters.

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Main Speaker / Source

The video is presented by an STM32H5 workshop instructor (likely an STMicroelectronics engineer or technical trainer) who provides both theoretical background and practical hands-on demonstration of the I3C interface using STM32H5 MCU and ST sensor hardware.