The World's First Ternary Computer

Technological concepts & main claims

• Core premise: Modern computing has relied on binary logic (0/1) for ~70 years, but the video argues this was largely a historical artifact of how early hardware (relays, vacuum tubes) worked.
• Ternary computing: Instead of two states, ternary logic uses three states per “trit” (described as -1, 0, +1). The video claims this can improve:
  • Efficiency
  • Data density
  • Math operations (e.g., subtraction/addition can be simpler because negative values don’t require an extra sign bit)
• Analog-adjacent idea: Ternary is described as between digital and analog—still discrete, but with more levels—potentially beneficial for AI efficiency.

Historical example (Soviet): Setun

The video recounts that Nikolay Brusentsov and Sergey Sobolev developed Setun, presented as the first ternary computer (unveiled 1958).

Setun features (as stated)

• Used 3 logic states: -1 (NO), 0, +1 (YES) (video phrasing varies slightly around details).
• Claimed cost and part reductions, including:
  • only ~2000 magnetic elements and ~100 germanium transistors
  • described as 10× cheaper than contemporary binary systems
  • ~30% fewer parts than a binary machine
• ~50 units built and shipped to research institutions (1959), but production was discontinued due to:
  • lack of ecosystem/political will
  • the world’s lock-in to binary (hardware + software stack)

Modern push: Huawei ternary chip

The video claims Huawei has demonstrated ternary logic feasibility with a new ternary chip at 7 nm.

How ternary is implemented (per the video)

• Classical transistors switch at one threshold (binary).
• To represent three states, the chip needs transistors (or devices) with two threshold levels to distinguish three distinct logic values.
• That requires rebuilding logic circuits and memory cells to store/operate with three states.

Logic-gate example: ternary AND

To illustrate how ternary inputs expand possibilities, the video uses a ternary AND gate example:

• Each input can be -1, 0, +1, giving 27 combinations (described as 3×3×3).
• Output behavior described includes:
  • If inputs are (+1, +1) → output +1
  • If inputs are (+1, 0) → output 0
  • If any case includes -1 → output -1 (as described)

Claim about compactness

Because each “bit” carries more information, ternary designs can be more compact (fewer wires/devices) and potentially more efficient.

Reported performance/power claims (as stated)

Based on Huawei’s patent (as described in the video), the chip allegedly achieves:

• 40% fewer devices
• 60% less power
• 20% faster operation

Caution about patents and unseen work

The video notes that patents are publicly visible and can be strategically limited; therefore, there may be additional unpublished progress behind the scenes.

Major obstacle: noise + ecosystem lock-in

Noise/precision challenge

Ternary devices must reliably distinguish three levels, so small noise or manufacturing variation can blur states and cause errors.

Software & toolchain dependency

The semiconductor ecosystem (memory formats, compilers, software assumptions) is built for binary, making large-scale deployment difficult.

Proposed hardware directions beyond silicon

The video suggests graphene and carbon nanotube transistors as promising for ternary logic:

• By adjusting nanotube diameter, the device can be tuned for three logic levels.
• Cites claims that graphene/carbon nanotubes can switch efficiently (low power, fast charge transport).
• Mentions an IEEE paper (as cited) reporting a ternary chip at 32 nm using carbon nanotubes with:
  • 45% less area
  • 30% less energy (for the same AI operations compared to binary)

Big-picture conclusion

• The video frames the question as whether ternary will replace binary.
• It argues ternary may instead run alongside binary, especially in domains where it offers clear benefits (notably AI efficiency at scale).
• The narrative echoes the historical pattern that major progress often comes from attempting fundamentally different approaches.
• A key motivation is data center and AI training power costs.

Reviews / guides / tutorials (function)

It functions like a technical deep dive into ternary logic, covering:

• historical development (Setun)
• hardware mechanism (multi-threshold transistors)
• example logic gate behavior (ternary AND)
• scalability constraints (noise + ecosystem lock-in)
• alternative materials (graphene/carbon nanotubes)

Main speakers / sources (as referenced)

• Video narrator / speaker: the creator of the channel (speaking in first person; not named).
• Historical sources mentioned:
  • Nikolay Brusentsov (engineer behind Setun)
  • Sergey Sobolev (mathematician introducing ternary mathematics)
  • IBM (mentioned as dominant binary producer historically)
  • Huawei (mentioned as releasing a ternary chip at 7 nm and tied to a patent)
• Research references mentioned:
  • IEEE papers (graphene/carbon nanotube ternary chip claims)
  • IEEE/TSMC/imec (mentioned as backing graphene/carbon nanotube directions for post-silicon)